深圳市锐视安科技有限公司

H5TQ1G63EFR

  VDD=VDDQ=1.5V +/- 0.075V •   Fully differential clock inputs (CK, CK) operation •   Differential Data Strobe (DQS, DQS) •   On chip DLL align DQ, DQS and DQS transition with CK  transition •   DM masks write data-in at the both rising and falling  edges of the data strobe •   All addresses and control inputs except data,  data strobes and data masks latched on the  rising edges of the clock •   Programmable CAS latency 6, 7, 8, 9, 10 supported •   Programmable additive latency 0, CL-1, and CL-2  supported •   Programmable CAS Write latency (CWL) = 5, 6, 7•   Programmable burst length 4/8 with both nibble     sequential and interleave mode •   BL switch on the fly •   8banks •    Average Refresh Cycle   (Tcase of 0  oC~ 95 oC) - 7.8 μs at 0oC ~ 85 oC                                                                - 3.9 μs at 85oC ~ 95 oC•   Auto Self Refresh supported •   JEDEC standard 78ball FBGA(x4/x8), 96ball FBGA(X16)•   Driver strength selected by EMRS •   Dynamic On Die Termination supported •   Asynchronous RESET pin supported •   ZQ calibration supported •   TDQS (Termination Data Strobe) supported (x8 only) •   Write Levelization supported •   8 bit pre-fetch 

H5TQ1G63EFR产品图片：

H5TQ1G63EFR参数：

型号：H5TQ1G63EFR

品牌：SK HYINX

存储温度：-55-100°

存储环境：常温

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